1 tm june 1996 hip0051 0.25a/50v octal low side power driver with serial bus control features ? eight open drain - ndmos low side drivers each capable of 250ma high voltage power bimos with low idle and standby current over-voltage clamp protection - each output . . . . . . . . . . . . . . . . . . . . . . . 50v typical serial data input, parallel output power drive common enable for output drivers and data storage register -40 o c to 85 o c operating range applications automotive and industrial systems solenoids, relays and lamp drivers logic and p controlled drivers robotic controls description the hip0051 is a logic controlled, eight channel octal low side power driver. as shown in the block diagram, the outputs are controlled via the serial data interface which allows the data to be shifted out, allowing control of other cascaded serial devices. the hip0051 is fabricated in a power bimos ic process, and is intended for use in automotive and other applications having a wide range of temperature and electrical stress conditions. it is particularly suited for driving lamps, displays, relays, and solenoids in applications where low operating power, high breakdown voltage, and high output current at high temperature is required. ordering information part number temp. range ( o c) package pkg. no. HIP0051IB -40 to 85 20 ld soic m20.3 pinout hip0051 (soic) top view block diagram 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 gnd v cc si dr0 dr1 dr2 nc dr3 en gnd gnd so dr7 dr6 lgnd dr5 dr4 sck str gnd sck output output driver (channel 1 of 8) dr#0 latch en (strobe) si so serial (spi) parallel (data is register input str (enable) q0 q1 q2 q3 q4 q5 q6 q7 strobed) when latched output 8-bit fn4155 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 absolute maximum ratings thermal information output voltage, v out (note 1). . . . . . . . . . . . . . . . . . . -0.3v to 40v input voltage, v in . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc + 0.3v logic supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v output clamp energy, 25 o c (5ms pulse). . . . . . . . . . . . . . . . . 75mj continuous output load current, i load (each output) . . . . . 0.25a continuous output current, i load (all outputs on, note 2). . 1.69a peak output current each output, other outputs off . . . . . . . . . . . . . . . . . . . . . 2a peak avalanche current (3ms duration) . . . . . . . . . . . . . . . . . . 1a operating conditions operating ambient temperature range, t a . . . . . . . -40 o c to 85 o c operating logic supply voltage range, v cc . . . . . +4.5v to +5.5v power output driver voltage range . . . . . . . . . . . . . . . . . 0 to v oc max. supply current, with 100ma each output . . . . . . . . . . . 100 a max. supply current, with no load, outputs off . . . . . . . . . 100 a logic input high voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7xv cc logic input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.2xv cc typical output r dson channel resistance . . . . . . . . . . . . . . . . 2 ? typical output rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 s typical output fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 s thermal resistance (typical, note 3) ja ( o c/w) soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range, t stg . . . . -55 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. notes: 1. the mosfet output drain is internally clamped with a drain-to-gate zener diode that turns-on the mosfet; holding the drain at the output clamp voltage v oc . 2. the maximum continuous current with all outputs on is limited by package dissipation. at 25 o c ambient temperature, the maximum equal current with all outputs on is 211ma in each output for a total of 1.69a. at a maximum ambient temperature of t a = 85 o c and r dson (max) = 3.5 ? , each output is limited to 152ma and the total current for all 8 outputs on is 8 x 152ma = 1.22a. 3. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications v cc = 4.5v to 5.5v, v batt = 8v to 16v, t a = -40 o c to 85 o c, unless otherwise specified. parameter symbol test conditions min typ max units outputs drivers (dr0 to dr7) output channel resistance r ds(on) output current = 200ma, t a =85 o c23.5 ? output clamping voltage v oc outputs off 42 50 58 v output clamping energy e oc 5ms pulse, t a = 25 o c75190mj peak output load currents, short duration i peak 100 s duration, each output, all outputs on, duty cycle 2% 0.85 - - a cold start-up lamp currents i lamp 5ms duration, each output, all outputs on, duty cycle 17% 0.3 - - a output off leakage current i off output voltage = 40v, t a =85 o c--0.210 a output rise time t rise load = 75 ? , 0.01 f (rc in parallel), v batt = 18v 0.5 4 30 s output fall time t fall 0.5 10 30 s output delay from strobe, high to low output transition t dhl 1410 s output delay from strobe, low to high output transition t dlh 0.2 2.6 10 s logic supply logic supply current, loaded i cc all outputs on, 200ma load at each output --100 a logic supply current, no load i cc all outputs off - - 100 a specifications hip0051
3 logic inputs (en , si, sck, str) threshold voltage at falling edge v t- v cc = 5v 10% 0.2v cc 0.3v cc -v threshold voltage at rising edge v t+ v cc = 5v 10% - 0.6v cc 0.7v cc v hysteresis voltage v h v t+ - v t- 0.85 1.4 2.25 v leakage current i lin v cc = 5v -10 -0.2 10 a leakage current i lin v cc = 0v -10 -0.1 10 a serial data clock (sck) frequency f sck --1.6mhz pulse width high t w(ckh) 175 27 - ns pulse width low t w(ckl) 175 27 - ns serial data in (si) input setup time t sui -1.175ns input hold time t hi -1.575ns strobe (str) strobe pulse width t w(s) 150 12 - ns min. clock to strobe delay t d(cs) 75 5 - ns serial data out (so) low level output voltage v ol sink current = 1.6ma - 0.2 0.4 v high level output voltage v oh source current = -1.6ma 3.7 4.4 - v propagation delay t p(cd) 75 260 - ns electrical specifications v cc = 4.5v to 5.5v, v batt = 8v to 16v, t a = -40 o c to 85 o c, unless otherwise specified. (continued) parameter symbol test conditions min typ max units figure 1. logic timing control specifications sck (clock) si (serial data in) str (strobe) drx so (serial data out) t w(sck) t w(sck) t sui t hi t d(cs) t w(s) t dlh t dhl t p(cd) t fall , t rise 10% 90% (power output driver) specifications hip0051
4 pin descriptions v cc - logic power supply the v cc pin is the positive 5v logic voltage supply input for the ic. the normal operating voltage range is 4.5 to 5.5v. when switched on, the por forces all outputs off. sck - serial clock sck is the clock input for the spi interface. output on/off control data is clocked into an eight stage shift register on the rising edge of an external clock. this input has a schmitt trigger. si - serial data in si is the serial data input pin for the spi interface. the eight power outputs are controlled by the serial data via the output data buffer. this input has a schmitt trigger. str - strobe for the spi interface when the str pin is high, data from the 8-bit shift register is passed into the output data buffers where it controls the on-off state of each output driver. the data is latched in the output data buffers on the trailing edge of the str pulse. this input has a schmitt trigger. so - serial data out the serial data out allows other ics to be serially cascaded. for example, a 10-bit led driver may be located behind the hip0051. a controlling microprocessor may then clock out 18 bits of information and simultaneously strobe both parts. the cascaded ics may be the same or different from the hip0051. dr0 to dr7 - outputs 0 thru 7 the drain output pins of the dmos power drivers are capable of sinking 250ma. en - enable the enable pin is an active low enable function for all eight output drivers. when en is high, drive from the output data buffer is held low and all output drivers are disabled. when en is low, the output drivers are enabled and data in the 8-bit shift register is transparent to the output data buffer. this input has a schmitt trigger. lgnd and gnd - ground lgnd is the logic input power supply ground pin. the gnd pins are common grounds for the power output drivers. the power supplies for the logic and power circuits require a common ground. to minimize ground bounce at the logic input, the external ground return path for the gnd pin should be separate from the lgnd pin. lgnd and gnd have com- mon substrate ground connections on the chip. output control table strobe 8-bit serial data (latched) output ?? d1 d2 d3 d4 d5 d6 d7 d8 dr1 dr2 dr3 dr4 dr5 dr6 dr7 dr8 ?? 00000000offoffoffoffoffoffoffoff ?? 1 0 0 0 0 0 0 0 on off off off off off off off ?? 11000000ononoffoffoffoffoffoff ?? 1 1 1 0 0 0 0 0 on on on off off off off off ?? 1 1 1 1 0 0 0 0 on on on on off off off off ?? 0 0 0 0 1 1 1 1 off off off off on on on on ?? 1 1 1 1 1 1 1 1 on on on on on on on on hip0051
5 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 hip0051 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m small outline plastic packages (soic) m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 0 o 8 o 0 o 8 o - rev. 0 12/93
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